Simulating CAPI Designs with PSLSE and Vivado

Following up on the Hello AFU tutorial, this post covers the process to bring simulate that design in Vivavo’s xsim.

Setting up PSLSE

Assuming readers may not have setup PSLSE before, I will start by cloning that down again and building it with support for use with Vivado.

First, I’ll just clone down the repo and enter it’s directory.

kwilke@kbawx:~/projects$ git clone https://github.com/ibm-capi/pslse
Cloning into 'pslse'...
remote: Counting objects: 2789, done.
remote: Compressing objects: 100% (11/11), done.
remote: Total 2789 (delta 0), reused 0 (delta 0), pack-reused 2778
Receiving objects: 100% (2789/2789), 954.75 KiB | 0 bytes/s, done.
Resolving deltas: 100% (1952/1952), done.
Checking connectivity... done.

Next, I’ll set the VPI_USER_H_DIR to point to the xsim include directory from my local Vivado installation and build the afu_driver, pslse and libcxl from the PSLSE repo.

kwilke@kbawx:~/projects/pslse$ export VPI_USER_H_DIR=/opt/Xilinx/Vivado/2015.4/data/xsim/include
kwilke@kbawx:~/projects/pslse$ cd afu_driver/src
kwilke@kbawx:~/projects/pslse/afu_driver/src$ make
 [CC]    afu_driver.o
...
 [CC]    libdpi.so
kwilke@kbawx:~/projects/pslse/afu_driver/src$ cd ../../pslse/
kwilke@kbawx:~/projects/pslse/pslse$ make
 [CC]    shim_host.o
 ...
 [CC]    pslse
kwilke@kbawx:~/projects/pslse/pslse$ cd ../libcxl/
kwilke@kbawx:~/projects/pslse/libcxl$ make
 [CC]    libcxl.o
...
 [AR]    libcxl.a 

Next I’ll add some symlinks to te psl_interface headers into my pslse/afu_driver/src directory to ease the library compilation via Vivado’s xsc.

kwilke@kbawx:~/projects/pslse/libcxl$ cd ../afu_driver/src/
kwilke@kbawx:~/projects/pslse/afu_driver/src$ ln -s ../../common/psl_interface.h .
kwilke@kbawx:~/projects/pslse/afu_driver/src$ ln -s ../../common/psl_interface_t.h .

Now PSLSE should be ready for us.



Compiling the DPI library and AFU

The next step is to enter the Hello AFU directory and build the AFU driver for Vivado.

kwilke@kbawx:~/projects/hello-afu$ xsc ~/projects/pslse/afu_driver/src/afu_driver.c
Multi-threading is on. Using 2 slave threads.
Running compilation flow
Done compilation
Done linking: "/home/kwilke/projects/hello-afu/xsim.dir/xsc/dpi.so"

I’ll create a symlink to the libdpi.so into my Hello AFU directory.

kwilke@kbawx:~/projects/hello-afu$ ln -s ~/projects/pslse/afu_driver/src/libdpi.so .

Next I’ll use xvlog to build the AFU code.

kwilke@kbawx:~/projects/hello-afu$ xvlog --sv *.sv *.v
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/kwilke/projects/hello-afu/afu.sv" into library work
INFO: [VRFC 10-311] analyzing module afu
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/kwilke/projects/hello-afu/capi.sv" into library work
INFO: [VRFC 10-443] port direction not specified for function/task, assuming input [/home/kwilke/projects/hello-afu/capi.sv:136]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/kwilke/projects/hello-afu/mmio.sv" into library work
INFO: [VRFC 10-311] analyzing module mmio
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/kwilke/projects/hello-afu/parity_afu.sv" into library work
INFO: [VRFC 10-311] analyzing module parity_afu
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/kwilke/projects/hello-afu/parity_workelement.sv" into library work
INFO: [VRFC 10-443] port direction not specified for function/task, assuming input [/home/kwilke/projects/hello-afu/parity_workelement.sv:27]
INFO: [VRFC 10-311] analyzing module parity_workelement
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/kwilke/projects/hello-afu/shift_register.sv" into library work
INFO: [VRFC 10-311] analyzing module shift_register
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/kwilke/projects/hello-afu/top.v" into library work
INFO: [VRFC 10-311] analyzing module top

Finally, I’ll use xelab to elaborate the design.

kwilke@kbawx:~/projects/hello-afu$ xelab -timescale 1ns/1ps -svlog ~/projects/pslse/afu_driver/verilog/top.v -sv_root . -sv_lib libdpi -debug all
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2015.4/bin/unwrapped/lnx64.o/xelab -timescale 1ns/1ps -svlog /home/kwilke/projects/pslse/afu_driver/verilog/top.v -sv_root . -sv_lib libdpi -debug all 
Multi-threading is on. Using 2 slave threads.
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/kwilke/projects/pslse/afu_driver/verilog/top.v" into library work
INFO: [VRFC 10-311] analyzing module top
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module work.shift_register
Compiling module work.shift_register(width=64)
Compiling module work.mmio
Compiling module work.shift_register(width=512)
Compiling module work.parity_workelement
Compiling module work.parity_afu
Compiling module work.afu
Compiling module work.top
Compiling package work.CAPI
Compiling package work.$unit_1
Built simulation snapshot work.top

We should now be in a good state to begin simulation.

Running the simulation

To kick off the simulation, I’ll point xsim to the project.

kwilke@kbawx:~/projects/hello-afu$ xsim -g work.top

****** xsim v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

start_gui

At this point the Vivado tools will come up and enter simulation for our project.

Vivado simulation window

Hitting the Run All button from the top (looks like a Play button with a square wave) it’ll start off the simulation and wait for a connection from PSLSE.

Simulation Console Output

I can now kick off PSLSE and it’ll connect to xsim and wait for a connection from my application.

Starting PSLSE with Vivado

At this time the master branch of PSLSE isn’t building libcxl.so, so I’ve pointed my application to the library of a previous build and it’s worked just fine.

Hello simulation in Vivado

Hooray! I now have my system setup to simulate CAPI designs in Vivado! I hope this post is useful for others working to get their CAPI designs simulated in Vivado, if you have any questions or comments please pass them my way!